From: johnh@macadam.mpce.mq.edu.au (John Haddy) Subject: Re: Help wanted Organization: Macquarie University Lines: 54 Distribution: world NNTP-Posting-Host: macadam.mpce.mq.edu.au In article <1993Apr20.071549.24839@csc.canberra.edu.au>, u934132@student.canberra.edu.au (Ogawa / Taro Stephen (ISE)) writes: |> Could someone please tell me if a 1/4 decoder is the same as a 1 to 4 |> demultiplexer. I know how to link 2 of these to get an 8 output circuit, |> but how do I link 5 of these to make a 1/16 multiplexer. Sorry if this |> seems like a lame question, but I'm only a newbie to electronics, and I |> have to do this circuit. Please make any mail as droolproof as possible. |> |> Thanx, |> Taro Ogawa |> (u934132@student.canberra.edu.au) A 1 of 4 decoder need not be the same as a 1 to 4 demultiplexer, although many commercial SSI implementations allow you to use one as such. Strictly, a 1 of 4 decoder need only take two lines in and make one output change state, according to the inputs. A demux, on the other hand, uses two control inputs to determine which of four outputs will reflect the state of the input signal. So there are three inputs required. A decoder can be used as a demux if it is equipped with an output enable input, since this can be used as the data input (e.g. when high, all outputs are high; when low, only the selected (by control inputs) output will be low). An eight way decoder is created by using the high order bit (bit 2) to select which of two four way demuxes is enabled. Thus you achieve your aim of having only one output of eight reflecting the input bits. Note that this method cannot be used to create a true eight way demux, since you have no data input (the enable line on a four way decoder) left once you commit the enable lines to their intended purpose. A sixteen way decoder obviously requires four, four-way decoders, plus a mechanism to enable only one of the four at a time. Therefore, use the fifth decoder, attached to the two high order bits, to provide the four enable lines. Of course, the two low order bits must be connected in parallel to the four final stage decoders. Please give me the credit when you submit your homework. JohnH ---------------------------------------------------------------------------- | _ |_ _ |_| _ _| _| Electronics Department |_| (_) | | | | | | (_| (_| (_| \/ School of MPCE ---------------------------------/- Macquarie University Sydney, AUSTRALIA 2109 Email: johnh@mpce.mq.edu.au, Ph: +61 2 805 8959, Fax: +61 2 805 8983 ----------------------------------------------------------------------------